DVP PCLK HSYNC Image Sensor Board Dothinkey Decoder Board

Image sensor board A27_MAX96706

Dothinkey's A27_MAX96706 decoder board supports DVP signal output and works with Dothinkey's MU960/UC930 Image Grabber to realize the image acquisition and data burning function of in-vehicle camera module.

What is DVP signal output?

DVP (Digital Video Port) is a traditional sensor output interface with parallel output mode, the data bit width of DVP interface can be 8bit, 10bit, 12bit, or 16bit, using CMOS level signals, and the maximum rate is about 96MHz. The maximum rate is approximately 96MHz.

The main signals of the DVP interface include:
PCLK (Pixel Clock): Pixel clock, each clock corresponds to one pixel data.
HSYNC (Horizontal Synchronization): Line synchronization signal, used to control the data transmission of each line.
VSYNC (Vertical Synchronization): frame synchronization signal, used to control the data transmission of each frame.
DATA: pixel data, exact bit width depends on ISP or baseband support.

Characteristics of the DVP interface include:
Parallel output: DVP uses parallel transmission, which is slower and has a lower bandwidth.
CMOS level signals: CMOS level signals are used instead of differential signals.

In practice, the DVP interface is commonly used to connect the image sensor and the image processing chip (ISP) for video data transmission and processing. For example, the ISP chip will provide an external clock input (MCLK or XCLK), and the PLL inside the sensor will calculate to generate the PCLK, the frequency of which is determined by the image's magnitude, frame rate and resolution.